Low power digital signal processing

This thesis introduces a novel approach to programmable and low power platform design for audio signal processing, in particular hearing aids. The proposed programmable platform is a heterogeneous multi-processor architecture consisting of small and simple instruction set processors called mini-cores as well as standard DSP/CPU-cores that communicate using message passing. The work has been based on a study of the algorithm suite covering the application domain. The observation of dominant tasks for certain algorithms (FIR, IIR, correlation, etc.) that require custom computational units and special data addressing capabilities lead to the design of low power mini-cores. The algorithm suite also consisted of less demanding and/or irregular algorithms (LMS, compression) that required sub-sample rate signal processing justifying the use of a DSP/CPUcore. The thesis also contributes to the recent trend in the development of intellectual property based design methodologies. The actual mini-core designs are parameterized in word-size, memory-size, etc. and can be instantiated according to the needs of the application at hand. They are intended as low power programmable building blocks for a standard cell synthesis based design flow leading to a system-on-chip. Two mini-cores targeting FIR and IIR type of algorithms have been designed to evaluate the concept. Results obtained from the design of a prototype chip demonstrate a power consumption that is only 1.5 – 1.6 times larger than commercial hardwired ASICs and more than 6 – 21 times lower than current state of the art low-power DSP processors. An orthogonal but practical contribution of this thesis is the test bench implementation. A PCI-based FPGA board has been used to equip a standard desktop PC with tester facilities. The test bench proved to be a viable alternative to conventional expensive test equipment. Finally, the work presented in this thesis has been published at several IEEE workshops and conferences [71, 70, 72], and in the Journal of VLSI Signal Processing [73].